Field of the Invention
This invention relates generally to the field of computer processors and software. More particularly, the invention relates to a method and apparatus for implementing proactive throttling of operations in a processor core to improve transitions between different power usage levels.
Description of the Related Art
Current core architectures (e.g., such as Intel Architecture (IA) cores) can switch very rapidly from low power activity to a high power activity. By way of example, a core may very quickly change from performing just one or a few microoperations (uOps) in period of time to many uOps over the same period of time based on fluctuations in the instruction stream. Such instantaneous load transition can cause excessive supply droops in real systems which may result in logic failures in the core logic critical paths, thereby limiting the performance of the chip.
FIG. 8 show an example of a simulated code trace current load 801 (equivalent in the present application to instantaneous power consumption) over time and a corresponding supply voltage fluctuations 802. The code in the illustrated example produces fast transients between low power code interrupts and high power code sections (termed “power virus” as they are designed to produce the maximum power from the core pipeline).
As can be seen from the figure, fast transitions of current load/power 801 induce noises in the supply voltage 802. In particular, a power supply “hazard droop” results in response to the transition between the low power interrupt and the high power virus code. In other words, the voltage source is unable to supply the needed voltage quickly enough to account for the increased load/power requirements of the high power virus code, potentially resulting in logic failures and/or decreased performance. Empirical testing (i.e., probing of the voltage supply using a scope) acknowledges these supply droops, as can be seen by the scope waveform overlaid on the simulated plot waveform (within the dashed box).
Prior solutions to address (or avoid) this problem focused on improving the resources devoted to the power delivery network, in order to minimize the droops caused by the core power transitions. However, these solutions are ineffective in new market segments where the system form factor and cost are becoming the key factors.
A few analog techniques have been employed to reduce power droops but these have been specific to the power supply active schemes of existing products, and therefore cannot be applied to products that utilize a power supply passive scheme (e.g., an external voltage regulator). Other techniques are implemented using architectural core features such as the Alloc Watchdog and reactive throttling schemes. For example, the Alloc Watchdog prompts for a higher voltage margin from the power control unit (PCU) when noticing high power instructions in the pipe. Until the higher margin is achieved, strong performance throttling safeguards against logic failures. The drawbacks of these techniques are significant performance loss until the increased voltage margin is maintained.
Reactive throttling reduces the core pipeline activity by introducing bubble patterns into the high power ports of the core (e.g., floating point math and memory transactions) when detecting a significant power consumption change (determined from the ongoing real time executed instructions in the pipe). The main limitation of this scheme (aside from significant throttling due to false triggering) is that by the time throttling is implemented (following detection and activation, the supply droop has reached close to its full magnitude. Consequently, the droop reduction achieved in practice has not been as large as desired.